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Verilog HDL

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    A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this brief, a new very-large-scale integrated (VLSI) integer transform architecture is proposed for the High Efficiency Video Coding (HEVC) encoder. The architecture is designed based on the signed bit-plane transform (SBT) matrices, which are derived from the bit-plane decompositions of the integer transform matrices in HEVC

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    Probability-Driven Multibit Flip-Flop Integration With Clock Gating

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these techniques into a single grouping algorithm and design flow enables further power savings. We study.

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    Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    The modular multiplication operation is the most time-consuming operation for number-theoretic cryptographic algorithms involving large integers, such as RSA and Diffie-Hellman. Implementations reveal that more than 75 percent of the time is spent in the modular multiplication function within the RSA for more than 1,024-bit moduli. There are fast multiplier architectures to minimize the delay and increase the throughput using parallelism and pipelining.

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    Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices.

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    Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to n/4 for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of (n + 1)/4. Therefore, a reduction of one unit in the maximum height is achieved.

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    A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this paper, a novel globally asynchronous locally synchronous (GALS) modeling and verification tool is introduced for xMAS circuits. The tool provides a structured environment for GALS in which organization of the modeling and verification enables it to handle a variety of implementation tasks facilitating a process which would otherwise be difficult for the end user

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    Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    A new radix-3 partitioning method of natural numbers, derived by the weight partition theory, is employed to build a multiplierless circuit that is well suited for multimedia filtering applications. The partitioning method allows conveniently premultiplying 32-b floating-point filter coefficients with the smallest set of parts composing an unsigned integer input.

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    Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 11 Months ago

    In this paper, an efficient recursive formulation is suggested for systolic implementation of canonical basis finite field multiplication over G F(2m) based on irreducible AOP. We have derived a recursive algorithm for the multiplication, and used that to design a regular and localized bit-level dependence graph (DG) for systolic computation.

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    Probabilistic Error Modeling for Approximate Adders

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Approximate adders are widely being advocated as a means to achieve performance gain in error resilient applications. In this paper, a generic methodology for analytical modeling of probability of occurrence of error and the Probability Mass Function (PMF) of error value in a selected class of approximate adders is presented, which can serve as performance metrics for the comparative analysis of various adders and their configurations.

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    LFSR-Based Generation of Multicycle Tests

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linearfeedback shift register, and whose primary input vectors are held constant during the application of a multicycle test. The goal of computing multicycle tests is to provide test compaction that reduces both the test application time and the test data volume. To avoid sequential test generation, the procedure uses a single-cycle test set to guide the computation of multicycle tests.

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    Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography.

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    An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    True random number generators (TRNGs) play a very important role in modern cryptographic systems. Fieldprogrammable gate arrays (FPGAs) form an ideal platform for hardware implementations

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    RoBA Multiplier A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the price of a small error. The proposed approach is applicable to both signed and unsigned multiplications.

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    DLAU A Scalable Deep Learning Accelerator Unit on FPGA

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications,

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    A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This brief presents a novel 4096-point radix-4 memorybased fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers.

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    Design of Efficient Multiplierless Modified Cosine-Based Comb Decimation Filters Analysis and Implementation

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper presents a computationally efficient design of modified cosine-based decimation filters. One of the main contributions of this paper is the proposal of a multiplierless finite impulse response low-order linear-phase filter to increase spurious signal rejection in the so-called folding bands. The resulting filters feature reduced computational complexity compared with other recent proposals

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    Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type of hard-decision decoder for Low-Density Parity-Check (LDPC) code, with improved error correction performance thanks to the introduction of deliberate random perturbation in the computing units. In the PGDBF, the random perturbation operates during the bit-flipping step, with the objective to avoid

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    Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Among the emerging technologies recently proposed as alternatives to the classic CMOS, quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultralow-power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits.

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    Overloaded CDMA Crossbar for Network-On-Chip

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    On-chip interconnects are the performance bottleneck in modern system-on-chips. Code-division multiple access (CDMA) has been proposed to implement on-chip crossbars due to its fixed latency, reduced arbitration overhead, and higher bandwidth. In CDMA, medium sharing is enabled in the code space by assigning a limited number of N-chip length orthogonal spreading codes to the processing elements sharing the interconnect.

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    High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Owing to their capacity-achieving performance and low encoding and decoding complexity, polar codes have received significant attention recently.

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    Design of Power and Area Efficient Approximate Multipliers

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability.

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    An Efficient O(N) Comparison-Free Sorting Algorithm

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this paper, we propose a novel sorting algorithm that sorts input data integer elements on-the-fly without any comparison operations between the data—comparison-free sorting. We present a complete hardware structure, associated timing diagrams, and a formal mathematical proof, which show an overall sorting time, in terms of clock cycles,

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    Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    VLSI realizations of digit-recurrence binary division usually use redundant representation of partial remainders and quotient digits. The former allows for fast carry-free computation of the next partial remainder, and the latter leads to less number of the required divisor multiples. In studying the previous relevant works, we have noted that the binary carrysave (CS) number system is prevalent in the representation of partial remainders, and redundant high radix representation of quotient digits is popular in order to reduce the cycle count. In this paper, we explore a design space containing four division architectures.

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    A General Digit-Serial Architecture for Montgomery Modular Multiplication

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented.

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    High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually needed. Previously, a technique named state-space transformation was presented to reduce the complexity of parallel LFSR architectures.

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    Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss.

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    Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Decimal X × Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix-10 X multiples. Some works require only [0, 5] × X via recoding digits of Y to one-hot representation of signed digits in [?5, 5].

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    A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes.

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper presents the design and implementation of memory-based fast Fourier transform (FFT) processors with generalized efficient, conflict-free address schemes. We unified the conflict-free address schemes of three different FFT lengths, including the single-power points, the common nonsingle-power points, and the nonsingle-power points applied with a prime factor algorithm. Though the three cases differ in terms of decomposition, they are all compatible with memory-based architecture by the way of the proposed address schemes.

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    On the VLSI Energy Complexity of LDPC Decoder Circuits

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Sequences of randomly generated bipartite configurations are analyzed; under mild conditions almost surely such configurations have minimum bisection width proportional to the number of vertices.

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    Reconfigurable Constant Multiplication for FPGAs

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This paper introduces a new heuristic to generate pipelined run-time reconfigurable constant multipliers for fieldprogrammable gate arrays (FPGAs). It produces results close to the optimum. It is based on an optimal algorithm which fuses already optimized pipelined constant multipliers generated by an existing heuristic called reduced pipelined adder graph (RPAG).

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    LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Due to their capacity-achieving property, polar codes have become one of the most attractive channel codes. To date, the successive-cancellation list (SCL) decoding algorithm is the primary approach that can guarantee outstanding error-correcting performance of polar codes

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    Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation.

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    Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Two digit-level finite field multipliers in F2m using redundant representation are presented. Embedding F2m in cyclotomic field F(n) 2 causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem.

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    Dual-Quality 4 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy.

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    Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for a digit-serial finite field multiplier in GF(2m). In the proposed design, a factoring technique is used to minimize switching power

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    Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders.

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    This brief introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic, and static complementary metal-oxide.

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    Register-Less NULL Convention Logic.

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm.

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    Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts.

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    Delay Analysis for Current Mode Threshold Logic Gate Designs

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy.

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    10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

    • B.Tech / M.Tech / M.Sc / Ph.D

    •  GANGADHAR.T

    • 12 Months ago

    We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell’s supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual

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