## Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

- B.Tech / M.Tech / M.Sc / Ph.D

- GANGADHAR.T

- 12 Months ago

In CMOS-based application-specific integrated
circuit (ASIC) designs, total power consumption is dominated
by dynamic power, where dynamic power consists of two major
components, namely, switching power and internal power. In this
paper, we present a low-power design for a digit-serial finite
field multiplier in GF(2m). In the proposed design, a factoring
technique is used to minimize switching power

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